In producing a semiconductor having highly increased degree of integration, the surface of the dielectric film should be completely planarized to realize multilayer wiring. As representative techniques of planarization known heretofore, studies have been made on, for instance, SOG (Spin-On-Glass) process, etch-back process (P. Elikins, K. Reinhardt, and R. Layer, “A planarization process for double metal CMOS using Spin-on Glass as a sacrificial layer”, Proceeding of 3rd International IEEE VMIC Conf., 100 (1986)), and lift-off process (K. Ehara, T. Morimoto, S. Muramoto, and S. Matsuo, “Planar Interconnection Technology for LSI Fabrication Utilizing Lift-off Process”, J. Electrochem. Soc., Vol.131, No.2, 419 (1984)).
Concerning the SOG process, although this is a planarization process utilizing the fluidity of the SOG film, the film itself is impossible to realize complete planarization. The etch-back process is the most widely employed technique; however, this process suffers the problem of generating dust on etching the resist and the dielectric film at the same time, and is not an easy technique concerning the point of dust control. In the lift-off process, the stencil material used cannot be completely dissolved on lift-off, and this leads to the generation of a problem of not realizing lifting off. Hence, this process is not put into practice due to incomplete controllability and production yield.
In the light of the aforementioned circumstances, CMP method is being attracting attention. This process comprises preferentially polishing the protruded portion of an irregular surface of the article to be polished with an abrasive by pressing the article to be polished against a rotating elastic pad, to thereby establish relative motion while supplying thereto a polishing liquid containing processing abrasives or a polishing liquid free from abrasives, and this process is widely employed thanks to the simplicity of the process.
For instance, Japanese Patent Laid-Open No. 11050/1996 discloses a polishing cloth characterized in that it comprises parts differing in surface hardness are formed by utilizing phase separation of a resin. However, the problems of scratches and dust adhesion remain to be solved. Furthermore, this process suffers the disadvantage that the homogeneous processing is difficult with respect to the thickness direction of the polishing cloth.
Further recently, fine irregularities that are present on the semiconductor wafer itself before subjecting it to the surface roughening process, i.e., those expressed as waviness, nanotopology and the like, which were conventionally unknown as problems, are now regarded problematic, and hence, practiced at present are the double face polishing, a process of carrying out polishing while flowing an alkali, and the like. However, in the CMP processes above, there are mentioned problems occurring on the surface of the article to be polished, such as the scratches, adhesion of dust, incomplete global planarity, and the like.
The polishing pads can be roughly classified into polishing pads for use in a conventional CMP in which polishing is carried out while supplying a polishing liquid containing abrasives (which is simply referred to hereinafter as “polishing pad” unless particularly specified), and pads with fixed abrasives, in which polishing is carried out while supplying a polishing liquid free of abrasives.
As common problems to be solved for the two types of pads above, there can be mentioned the generation of scratches and the adhesion of dust.
With respect to the so-called dishing and erosion on polishing, it is said that pads with fixed abrasives are superior, however, the problems of the scratches and the adhesion of dust that generate on the surface of the article to be polished remain unsolved.
In case the adhesion of dust or scratches generate on the polishing surface of, for instance, interlayer dielectric film and the like, step failure and the like may generate on forming interconnection using an Al based metal and the like in the later process, and this may lead to the generation of a problem of causing loss of reliability, such as the degradation in the resistance against electromigration. Otherwise, on polishing a non-magnetic substrate for HDD (Hard Disk Drive) and the like, this causes a drop in reproduced signals, such as dropouts. The generation of scratches are believed to be attributed to the agglomerates due to poor dispersion of abrasives. In particular, the polishing slurry using alumina as the abrasive grains, which is employed in the CMP of metallic films, suffers poor dispersibility, and is far from complete in preventing scratches from generating. Concerning dust adhesion, even the cause thereof is yet unknown.
In common sense, the use of a hard polishing pad is preferred for improving global planarity; however, since dust adhesion or scratches tend to form more easily by the use of such hard polishing pad, it is believed impossible to satisfy both requirements at the same time. For instance, although such attempts are disclosed in International Patent Publication No. 500622/1996 or in Japanese Patent Laid-Open No. 2000-34416, prevention of dust adhesion and scratches is not concurrent with the planarization characteristics.
In the light of such circumstances, an object of the present invention is, particularly, to reduce dust adhesion on the surface of the polished article. Another object of the present invention is to reduce the generation of scratches, while yet achieving favorable planarization characteristics at the same time.
Furthermore, another object is to remove, by a simple polishing method, fine irregularities of the semiconductor wafer itself before subjecting it to the surface roughening process, i.e., those expressed as waviness, nanotopology and the like.